What is SPEF (Standard Parasitic Exchange Format)?

In the field of Very Large Scale Integration (VLSI) design, a finished semiconductor chip's performance is not only determined by its logical functionality but is also significantly affected by physical phenomena that occur on the tiny wires, or interconnects, inside the chip.

These physical phenomena are known as parasitic effects, primarily manifesting as resistance (R), capacitance (C), and sometimes inductance (L) of the interconnects.

Since these parasitic elements directly impact signal propagation delay, power consumption, and noise, accurately extracting and analyzing this information is crucial for successfully designing and verifying high-performance chips.

To address this need, various files that contain parasitic values have emerged, with SPEF and DSPF being the most common. This post will focus on SPEF (Standard Parasitic Exchange Format), which is defined by the IEEE 1481 standard.

What is SPEF?

SPEF is an IEEE standard for representing parasitic information of an integrated circuit's interconnects in an ASCII text format. Specifically, this format is defined in the IEEE 1481-1999 standard.

An SPEF file typically contains the R, C, and L values obtained by an extraction tool during the chip layout stage (after the physical design is completed). It plays a critical role in modern VLSI design flows for the following reasons:

• Standard for Information Exchange: SPEF acts as a universal language that allows for the efficient and accurate exchange of parasitic information between various EDA (Electronic Design Automation) tools, such as placement and routing tools, static timing analysis tools, and power analysis tools. This ensures seamless interoperability, regardless of whether a designer uses tools from Synopsys or Cadence.
• Accurate Verification: Based on the extracted parasitic information, designers can precisely predict and simulate the actual chip's timing delay, power consumption, and signal integrity. This minimizes design errors and ensures product reliability.
• Design Convergence: Analyzing parasitic information helps designers identify design bottlenecks and optimize the design to improve them. This is essential for meeting circuit performance goals.

The Four Main Sections of a Typical SPEF File

An SPEF file is structured into four main sections to systematically organize the vast amount of circuit information. It's similar to how an academic paper is divided into an introduction, methodology, results, and conclusion.

• Header Section: This is like the file's "cover page." It contains essential metadata such as the design name, information about the extraction tool, the base units used (e.g., for time, capacitance, and resistance), and the file creation date. The unit information in this section is extremely important for subsequent analysis.
• Name Map Section: This section maps long names (e.g., instance or net names) within the design to shorter numeric IDs to efficiently reduce the file size. While not mandatory, this mapping significantly enhances file efficiency for large-scale designs.
• Top-Level Port Section: This section lists the top-level ports of the design and specifies the direction of each port (Input, Output, or Bidirectional). It is used to define the interface of the design hierarchy.
• Main Parasitic Description Section: This is the "main body" of the file, providing detailed parasitic information, including actual resistance, capacitance, and inductance, for each net. This section is further divided into subsections that describe the connections of the R, C, and L values.

Basic Syntax and Example

SPEF is a text-based format, and to be readable by humans and parsable by programs, it follows a few basic syntax rules:

• Keywords: Most SPEF keywords start with an asterisk (*). For example, *R_UNIT is used for the resistance unit, and *D_NET is used to start the net information.
• Comments:
  • Single-line comments begin with // and continue to the end of the line.
  • Multi-line comments are enclosed in /* and ***/**.

Example SPEF File

Here is an example of an SPEF file for a hypothetical design called "my_chip," containing parasitic information for a net named "data_path/reg1/q_out_net." The time unit is NS, capacitance is PF, and resistance is KOHM.

*SPEF "IEEE 1481-1999"
*DESIGN "my_chip"
*DATE "Fri Jul 20 22:35:00 2025"
*VENDOR "Example EDA Tool Inc."
*PROGRAM "ParasiticExtractor_v1.0"
*VERSION "1.0.0"
*DESIGN_FLOW "COUPLING C" "PIN_CAP NONE" "NAME_SCOPE LOCAL"
*DIVIDER /*DELIMITER :*/
*BUS_DELIMITER []
*T_UNIT 1 NS
*C_UNIT 1 PF
*R_UNIT 1 KOHM
*L_UNIT 1 HENRY // Inductance unit is declared, but often not used in digital designs
---
*NAME_MAP
*1 data_path/reg1/q_out_net
*2 data_path/buf_inst/A
*3 data_path/xor_gate/B
*4 data_path/next_stage_reg/D
*5 data_path/clk_gen/clk_out_net // Example of a coupled net
*6 U1/Z // Node name for the driver output
*7 U2/A // Node name for the first load input
*8 U3/B // Node name for the second load input
---
*PORTS
*top_input I
*top_output O
---
*D_NET *1 0.0523 // Net: data_path/reg1/q_out_net, Total Capacitance: 0.0523 PF
*CONN
*I *6 O *C 100.5 200.5 *D DFF_X1 // Driver: U1's Z pin (output) at coord (100.5, 200.5)
*I *7 I *C 110.0 210.0 *L 0.0025 *D BUF_X2 // Load 1: U2's A pin (input) at coord (110.0, 210.0), load cap 0.0025 PF
*I *8 I *C 125.0 225.0 *L 0.0030 *D XOR_X1 // Load 2: U3's B pin (input) at coord (125.0, 225.0), load cap 0.0030 PF
*I *4 I *C 150.0 250.0 *L 0.0040 *D REG_DFF // Load 3: U4's D pin (input) at coord (150.0, 250.0), load cap 0.0040 PF
*CAP
*1 *6 0.0050 // Lumped capacitance to ground at driver output node *6 (U1/Z)
*2 *7 0.0030 // Lumped capacitance to ground at load 1 input node *7 (U2/A)
*3 *8 0.0035 // Lumped capacitance to ground at load 2 input node *8 (U3/B)
*4 *4 0.0045 // Lumped capacitance to ground at load 3 input node *4 (U4/D)
*5 *6 *7 0.0100 // Coupling capacitance between driver output *6 and load 1 input *7
*6 *7 *8 0.0080 // Coupling capacitance between load 1 input *7 and load 2 input *8
*7 *1 *5 0.0150 // Coupling capacitance between this net (*1) and clock net (*5)
*RES
*1 *6 *7 0.020 // Resistance between driver output *6 and load 1 input *7
*2 *6 *8 0.030 // Resistance between driver output *6 and load 2 input *8
*3 *6 *4 0.045 // Resistance between driver output *6 and load 3 input *4
*END

This file and its corresponding explanation show how SPEF details various parasitic values:

• *SPEF "IEEE 1481-1999": Specifies that the file adheres to the IEEE 1481-1999 standard.
• *DESIGN "my_chip": The name of the design.
• *T_UNIT 1 NS, *C_UNIT 1 PF, *R_UNIT 1 KOHM: Sets the units for time (nanoseconds), capacitance (picofarads), and resistance (kilohms).
• *L_UNIT 1 HENRY: The unit for inductance. In many digital designs, this is declared but often not used.
• *NAME_MAP: Maps long names to shorter numbers. For example, data_path/reg1/q_out_net is now referred to as *1.
• *D_NET *1 0.0523: Begins the detailed parasitic information for net *1, indicating a total capacitance of 0.0523 PF.
• *CONN: Lists the pins connected to this net. The first entry specifies that *6 is the driver (output, O) pin of the DFF_X1 cell type.
• *CAP and *RES: These sections provide detailed capacitance and resistance information, including lumped capacitance to ground and coupling capacitance between different nodes. For example, 5 *6 *7 0.0100 shows a coupling capacitance of 0.0100 PF between pin *6 and pin *7. 1 *6 *7 0.020 shows a resistance of 0.020 KOHM between the same pins.
• *END: Marks the end of the parasitic information for net *1.

Importance in Chip Design

One of the most critical moments in chip design is when you perform the initial Post-Layout Static Timing Analysis (STA), which requires an SPEF file. This first SPEF file is often called the 'First Cap'.

Post-Layout STA is a crucial sign-off step performed at the very end of the chip design process, and it is notoriously difficult to pass. Based on the timing results from the first Post-Layout STA, you must make a critical decision:

1. Perform an ECO (Engineering Change Order).
2. Rerun P&R (Place and Route).
3. Rerun Synthesis.
4. Modify the Verilog code.
5. Modify the architecture.
6. Change the fabrication process itself.
7. Lower the specifications.

This is the first time you see the timing results for the architecture and Verilog code. If there are numerous hold violations, you might have to go all the way back to the RTL design. Otherwise, the back-end team may need to add buffers or change metal layers, which can be costly.

In the typical design flow: Architecture -> RTL -> Synthesis -> Pre-Layout STA -> P&R -> Post-Layout STA, parasitic extraction occurs right after P&R. Some call this process "Cap extraction" or "RC extraction," though "RLC extraction" is rarely used.

Why are R and C dominant, and L is often omitted?

While SPEF can include R, C, and L values, most digital VLSI designs primarily consist of R and C, with L (inductance) often being omitted. There are several good reasons for this common practice.

1. Frequency and Design Domain Impact

• The effect of inductance becomes more prominent at higher operating frequencies. Most digital circuits operate at relatively low frequencies, where the impact of resistance and capacitance on signal delay and waveform distortion is overwhelmingly dominant.
• Inductance is extremely important in specific domains, such as high-frequency (RF) or high-speed interface designs. However, for general digital logic design, its effect is often considered insignificant and can be ignored without a major impact on the design.

2. Complexity of Extraction and Simulation

• Accurately extracting inductance, particularly mutual inductance, is significantly more complex and computationally expensive than extracting R and C. This is because inductance is influenced by electromagnetic interactions with all surrounding conductors.
• Including inductance in simulations can cause the simulation time to increase exponentially, making it impractical for large-scale digital chips. This directly impacts the time-to-market.

3. Data Volume and Tool Efficiency

• Including inductance information would make SPEF files even more massive, increasing the burden on storage and processing.
• Many established EDA tools and design flows are already optimized for R and C modeling and analysis. Inductance extraction and analysis capabilities are often provided by specialized tools for high-frequency design or require additional settings or licenses in general-purpose tools.

Due to these reasons, most digital designs rely on R and C information for an accurate and efficient design and verification flow.

However, as technology advances and operating frequencies continue to rise, the importance of inductance is growing.

Some cutting-edge designs are now beginning to extract and analyze inductance for specific critical nets.